View STA320_438506.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STA320
2.1 MULTICHANNELS DIGITAL AUDIO PROCESSOR WITH DDXTM
1

FEATURES 2.1 Channels of 24-bit DDXTM >100dB SNR and Dynamic Range Selectable 32kHz-192kHz Input Sample Rates I2C control with Selectable Device Address Digital Gain/Attenuation +48dB to -90dB in 0.5dB steps Soft Volume Update Individual Channel and Master Gain/ Attenuation Dual Independent Limiters/Compressors Dynamic Range Compression or Anti-Clipping Modes AutoModesTM: - 7 Preset Crossover filters - 32 Preset EQ Settings - Auto Volume Controlled Loudness - 3 Preset Volume Curves - 2 Preset Anti-Clipping Modes - Preset Nighttime Listening Mode - Preset TV AGC Individual Channel and Master Soft and Hard Mute Independent Channel Volume and DSP Bypass Automatic Zero-Detect Mute Automatic Invalid Input Detect Mute 2-Channel I2S Input Data Interface Input and Output Channel Mapping 4 28-bit User Programmable Biquads (EQ) per channel Bass/Treble Tone Control DC Blocking Selectable High-Pass Filter Selectable De-emphasis
Figure 1. Package
SO28
Table 1. Order Code
Part Number STA320 Package SO28

Post-EQ User Programmable mix User Programmable 2.1 Bass Management Sub Channel Mix into Left and Right Channels Advanced AM Interference Frequency Switching and Noise Suppression Modes Selectable High or Low Bandwidth Noise Shaping Topologies Variable Max Power Correction for lower fullpower THD 3 or 4 Output Routing Configurations Selectable Clock Input Ratio 96kHz Internal Processing Sample Rate, 24 to 28-bit precision DESCRIPTION
2
The STA320 is a single chip solution for digital audio processing and control in 2.1-channel applications. It provides output capabilities for DDXTM (Direct Digital Amplification). In conjunction with a DDXTM power device, it provides high-quality, high-efficiency, all digital amplification.
November 2005
This is preliminary information on a new product now in development. Details are subject to change without notice.
REV. 1 1/37
STA320
Figure 2. PIN CONNECTION (Top view)
SA DDX1A DDX1B DDX2A DDX2B RESET SCL SDA RESERVED FILTER_PLL XTI GNDA VddA SDI_12
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D04AU1550
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND TWARN FAULT OCDETECT TRI-STATE EAPD DDX3B DDX3A PWDN Vdd Vdd GND BICKI LRCKI.
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol VDD VDDA Vi Vo Tstg Tamb 3.3V I/O Power Supply 3.3V Logic Power Supply Voltage on input pins Voltage on output pins Storage Temperature Ambient Operating Temperature Parameter Value -0.5 to 4 -0.5 to 4 -0.5 to (VDD+0.5) -0.5 to (VDD+0.3) -40 to +150 -20 to +85 Unit V V V V C C
Table 3. THERMAL DATA
Symbol Rthj-amb Parameter Thermal resistance Junction to Ambient Value 85 Unit C/W
Table 4. RECOMMENDED DC OPERATING CONDITIONS
Symbol VDD VDDA Tj I/O Power Supply Logic Power Supply Operating Junction Temperature Parameter Value 3.0 to 3.6 3.0 to 3.6 -20 to +125 Unit V V C
2/37
STA320
Table 5. PIN FUNCTION
Pin N 1 2 3 4 5 6 7 8 Name SA DDX1A DDX1B DDX2A DDX2B RESET SCL SDA Type I O O O O I I I/O Description IC Address selector Channel 1 DDX Output A Channel 1 DDX Output B Channel 2 DDX Output A Channel 2 DDX Output B Global reset (active low) IC Serial Clock IC Serial Data Pad Type CMOS Input Buffer with Pull-Down 3.3V Capable TTL 4mA Output Buffer 3.3V Capable TTL 4mA Output Buffer 3.3V Capable TTL 4mA Output Buffer 3.3V Capable TTL 4mA Output Buffer 5V Tolerant TTL Schmitt Trigger Input Buffer 5V Tolerant TTL Schmitt Trigger Input Buffer Bidirectional Buffer: 5V Tolerant TTL Schmitt Trigger Input; 3.3V Capable 2mA Slew-rate controlled Output.
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
RESERVED FILTER_PLL XTI GNDA VddA SDI_12 LRCKI BICKI GND Vdd Vdd PWDN DDX3A DDX3B EAPD TRI-STATE OCDETECT FAULT TWARN GND
-I I
Test pin to be externally connected to Ground Connection to PLL_filter PLL Input clock Analog Ground 3.3V Analog Power Supply Voltage Analog Pad 5V Tolerant TTL Schmitt Trigger Input Buffer Analog Ground 3.3V Analog Power Supply Voltage 5V Tolerant TTL Input Buffer 5V Tolerant TTL Input Buffer 5V Tolerant TTL Input Buffer Digital Ground 3.3V Digital Power Supply Voltage 3.3V Digital Power Supply Voltage 5V Tolerant TTL Schmitt Trigger Input Buffer 3.3V Capable TTL 4mA Output Buffer 3.3V Capable TTL 4mA Output Buffer 3.3V Capable TTL 4mA Output Buffer 3.3V Capable TTL 4mA Output Buffer 5V Tolerant TTL Input Buffer 5V Tolerant TTL Input Buffer 5V Tolerant TTL Input Buffer Digital Ground
I I I I/O I/O I/O I O O O O I I I I/O
IS Serial Data Channels 1 & 2 IS Left/Right Clock IS Serial Clock Digital Ground 3.3V Digital Power Supply Voltage 3.3V Digital Power Supply Voltage Device Powerdown Channel 3 DDX Output A Channel 3 DDX Output B External Amp Power Down Tri-state output to Power block Over-current Indicator Power Fault Indicator Thermal Warning Indicator Digital Ground
3/37
STA320
3 ELECTRICAL CHARACTERISTCS (VDD3 = 3.3V 0.3V; VDDA = 3.3V 0.3V; TAMB = 0 TO 70 C; UNLESS OTHERWISE SPECIFIED)
Table 6. GENERAL INTERFACE ELECTRICAL CHARACTERISTICS
Symbol Iil Iih IOZ Vesd Parameter Low Level Input no pull-up High Level Input no pull-down Tristate output leakage without pullup/down Electrostatic Protection Test Condition Vi = 0V Vi = VDD3 Vi = VDD3 Leakage < 1A 2000 Min. Typ. Max. 1 2 2 Unit A A A V Note 1 1 1 2
Note 1: The leakage currents are generally very small, < 1na. The values given here are maximum after an electrostatic stress on the pin. Note 2: Human Body Model
Table 7. DC ELECTRICAL CHARACTERISTICS: 3.3V BUFFERS
Symbol VIL VIH VILhyst VIHhyst Vhyst Vol Voh Parameter Low Level Input Voltage High Level Input Voltage Low Level Threshold High Level Threshold Schmitt Trigger Hysteresis Low Level Output High Level Output IoI = 100uA Ioh = -100uA Ioh = -2mA VDD3-0.2 2.4 Input Falling Input Rising 2.0 0.8 1.3 0.3 1.35 2.0 0.8 0.2 Test Condition Min. Typ. Max. 0.8 Unit V V V V V V V V
4
I2C BUS SPECIFICATION
The STA320 supports the I2C protocol via the input ports SCL and SDA_IN (Master to Slave) and the output port SDA_OUT (Slave to Master). This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA320 is always a slave device in all of its communications. It supported up to 400KB/sec rate (fast-mode bit rate). 4.1 COMMUNICATION PROTOCOL 4.1.1 Data Transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition. 4.1.2 Start Condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.
4/37
STA320
4.1.3 Stop Condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA320 and the bus master. 4.1.4 Data Input During the data input the STA320 samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. 4.2 DEVICE ADDRESSING To start communication between the master and the STA320, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first) corresponding to the device select address and read or write mode. The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA320 the I2C interface has two device addresses depending on the SA port configuration, 0x34 when SA = 0, and 0x36 when SA = 1. The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0 for write mode and 0 for write mode. After a START condition the STA320 identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address. 4.3 WRITE OPERATION Following the START condition the master sends a device select code with the RW bit set to 0. The STA320 acknowledges this and the writes for the byte of internal address. After receiving the internal byte address the STA320 again responds with an acknowledgement. 4.3.1 Byte Write In the byte write mode the master sends one data byte, this is acknowledged by the STA320. The master then terminates the transfer by generating a STOP condition. 4.3.2 Multi-byte Write The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer. Figure 3. Write Mode Sequence
ACK BYTE WRITE START DEV-ADDR SUB-ADDR ACK DATA IN ACK
RW
STOP
ACK MULTIBYTE WRITE START DEV-ADDR SUB-ADDR
ACK DATA IN
ACK DATA IN
ACK
RW
STOP
5/37
STA320
Figure 4. Read Mode Sequence
ACK CURRENT ADDRESS READ START
NO ACK
DEV-ADDR
DATA
RW ACK ACK SUB-ADDR
STOP ACK DEV-ADDR DATA NO ACK
RANDOM ADDRESS READ START
DEV-ADDR
RW RW= ACK HIGH DEV-ADDR DATA ACK
START
RW ACK DATA DATA NO ACK
STOP
SEQUENTIAL CURRENT READ START
STOP ACK ACK SUB-ADDR DEV-ADDR ACK DATA ACK DATA ACK DATA NO ACK
SEQUENTIAL RANDOM READ START
DEV-ADDR
RW
START
RW
STOP
5
REGISTER SUMMARY
Table 8. Register Summary
Addr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B Name ConfA ConfB ConfC ConfD ConfE ConfF Mute Mvol C1Vol C2Vol C3Vol Auto1 Auto2 Auto3 C1Cfg C2Cfg C3Cfg Tone L1ar L1atrt L2ar L2atrt Cfaddr B1cf1 B1cf2 B1cf3 B2cf1 B2cf2 C1B23 C1B15 C1B7 C2B23 C2B15 C1B22 C1B14 C1B6 C2B22 C2B14 C1OM1 C2OM1 C3OM1 TTC3 L1A3 L1AT3 L2A3 L2AT3 C1OM0 C2OM0 C3OM0 TTC2 L1A2 L1AT2 L2A2 L2AT2 C1LS1 C2LS1 C3LS1 TTC1 L1A1 L1AT1 L2A1 L2AT1 CFA5 C1B21 C1B13 C1B5 C2B21 C2B13 D7 FDRB C2IM OCRB MME SVE EAPD QFILT MV7 C1V7 C2V7 C3V7 AMPS XO3 XO2 D6 TWAB C1IM CSZ4 ZDE ZCE PWDN QXEN MV6 C1V6 C2V6 C3V6 MV5 C1V5 C2V5 C3V5 AMGC1 XO1 D5 TWRB DSCKE CSZ3 DRC DCCV ECLE IR1 SAIFB CSZ2 BQL PWMS LDTE TFRB MV4 C1V4 C2V4 C3V4 AMGC0 XO0 PEQ4 C1LS0 C2LS0 C3LS0 TTC0 L1A0 L1AT0 L2A0 L2AT0 CFA4 C1B20 C1B12 C1B4 C2B20 C2B12 D4 IR0 SAI3 CSZ1 PSL AME BCLE C3M MV3 C1V3 C2V3 C3V3 AMV1 AMAM2 PEQ3 C1BO C2BO C3BO BTC3 L1R3 L1RT3 L2R3 L2RT3 CFA3 C1B19 C1B11 C1B3 C2B19 C2B11 D3 D2 MCS2 SAI2 CSZ0 DSPB NSBW IDE C2M MV2 C1V2 C2V2 C3V2 AMV0 AMAM1 PEQ2 C1VBP C2VBP C3VBP BTC2 L1R2 L1RT2 L2R2 L2RT2 CFA2 C1B18 C1B10 C1B2 C2B18 C2B10 BTC1 L1R1 L1RT1 L2R1 L2RT1 CFA1 C1B17 C1B9 C1B1 C2B17 C2B9 BTC0 L1R0 L1RT0 L2R0 L2RT0 CFA0 C1B16 C1B8 C1B0 C2B16 C2B8 D1 MCS1 SAI1 OM1 DEMP MPC OCFG1 C1M MV1 C1V1 C2V1 C3V1 AMEQ1 AMAM0 PEQ1 C1EQBP C2EQBP D0 MCS0 SAI0 OM0 HPB MPCV OCFG0 MMute MV0 C1V0 C2V0 C3V0 AMEQ0 AMAME PEQ0 C1TCB C2TCB
6/37
STA320
Table 8. Register Summary (continued)
Addr 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 Name B2cf3 A1cf1 A1cf2 A1cf3 A2cf1 A2cf2 A2cf3 B0cf1 B0cf2 B0cf3 Cfud MPCC1 MPCC2 DCC1 DCC2 FDRC1 FDRC2 Status BC0 BS0 BS1 B1 B2 T MPCC15 MPCC7 DCC15 DCC7 FDRC15 FDRC7 PLLUL RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES MPCC14 MPCC6 DCC14 DCC6 FDRC14 FDRC6 MPCC13 MPCC5 DCC13 DCC5 FDRC13 FDRC5 MPCC12 MPCC4 DCC12 DCC4 FDRC12 FDRC4 D7 C2B7 C3B23 C3B15 C3B7 C4B23 C4B15 C4B7 C5B23 C5B15 C5B7 D6 C2B6 C3B22 C3B14 C3B6 C4B22 C4B14 C4B6 C5B22 C5B14 C5B6 D5 C2B5 C3B21 C3B13 C3B5 C4B21 C4B13 C4B5 C5B21 C5B13 C5B5 D4 C2B4 C3B20 C3B12 C3B4 C4B20 C4B12 C4B4 C5B20 C5B12 C5B4 D3 C2B3 C3B19 C3B11 C3B3 C4B19 C4B11 C4B3 C5B19 C5B11 C5B3 RA MPCC11 MPCC3 DCC11 DCC3 FDRC11 FDRC3 RES RES RES RES RES RES D2 C2B2 C3B18 C3B10 C3B2 C4B18 C4B10 C4B2 C5B18 C5B10 C5B2 R1 MPCC10 MPCC2 DCC10 DCC2 FDRC10 FDRC2 RES RES RES RES RES RES D1 C2B1 C3B17 C3B9 C3B1 C4B17 C4B9 C4B1 C5B17 C5B9 C5B1 WA MPCC9 MPCC1 DCC9 DCC1 FDRC9 FDRC1 FAULT RES BS9 RES RES RES RES D0 C2B0 C3B16 C3B8 C3B0 C4B16 C4B8 C4B0 C5B16 C5B8 C5B0 W1 MPCC8 MPCC0 DCC8 DCC0 FDRC8 FDRC0 TWARN RES BS8 RES RES RES RES
OCWARN TFAULT
5.1 Configuration Register A (address 00h)
D7 FDRB 0 D6 TWAB 1 D5 TFRB 1 D4 IR1 0 D3 IR0 0 D2 MCS2 0 D1 MCS1 1 D0 MCS0 1
5.1.1 Master Clock Select
BIT 0 1 2 R/W R/W R/W R/W RST 1 1 0 NAME MCS0 MCS1 MCS2 DESCRIPTION Master Clock Select : Selects the ratio between the input I2S sample frequency and the input clock.
The STA320 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, 96kHz, Therefore the internal clock will be: - 32.768Mhz for 32kHz - 45.1584Mhz for 44.1khz, 88.2kHz and 176.4kHz - 49.152Mhz for 48kHz, 96kHz, and 192kHz The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency(fs). The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (Input Rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determine the oversampling ratio used internally.
7/37
STA320
Table 9.
Input Sample Rate fs (kHz) IR 000 32, 44.1, 48 88.2, 96 176.4, 192 00 01 1X 768fs 384fs 384fs 001 512fs 256fs 256fs MCS(2..0) 010 384fs 192fs 192fs 011 256fs 128fs 128fs 100 128fs 64fs 64fs 101 576fs x x
5.1.2 Interpolation Ratio Select
BIT 4..3 R/W R/W RST 00 NAME IR(1..0) DESCRIPTION Interpolation Ratio Select: Selects internal interpolation ratio based on input I2S sample frequency
The STA320 has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through). or provides a 2 times downsample. The IR bits determine the oversampling ratio of this interpolation. IR bit settings as a function of Input Sample Rate Table 10.
Input Sample Rate Fs (kHz) 32 44.1 48 88.2 96 176.4 192 IR(1,0) 00 00 00 01 01 10 10 1st Stage Interpolation Ratio 2 times oversampling 2 times oversampling 2 times oversampling Pass-Through Pass-Through 2 times oversampling 2 times oversampling
Example: IR = 00, MCS = 011 (Default value): XTI = 256 x fs = 8.192MHz (fs=32KHz) or 11.2896MHz (fs=44.1KHz) or 12.288MHz (fs=48KHz)
5.1.3 Thermal Warning Recovery Bypass
BIT 5 R/W R/W RST 1 NAME TWRB DESCRIPTION Thermal-Warning Recovery Bypass: 0 - Thermal warning Recovery enabled 1 - Thermal warning Recovery disabled
If the Thermal Warning Adjustment is enabled (TWAB=0), then the Thermal Warning Recovery will determine if the -3dB adjustment is removed when Thermal Warning is negative. If TWRB=0 and TWAB=0, then when a thermal warning disappears the -3dB adjustment will be removed and the gain will be added back to the system. If TWRB=1 and TWAB=0, then when a thermal warning disappears the -3dB adjustment will remain until TWRB is changed to zero or the device is reset.
8/37
STA320
5.1.4 Thermal Warning Adjustable Bypass
BIT 6 R/W R/W RST 1 NAME TWAB DESCRIPTION Thermal-Warning Recovery Bypass: 0 - Thermal warning Recovery enabled 1 - Thermal warning Recovery disabled
The on-chip STA320 Power Output block provides feedback to the digital controller using inputs to the Power Control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period of time greater than 400ms, the power control block will force a -3dB adjustment to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning volume adjustment is applied, it remains in this state until reset. 5.1.5 hermal Warning Adjustable Bypass
BIT 7 R/W R/W RST 0 NAME FDRB DESCRIPTION Fault -Detector Recovery Bypass: 0 - Fault Detector Recovery enabled 1 - Fault Detector Recovery disabled
The on-chip STA320 Power Output block provides feedback to the digital controller using inputs to the Power Control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block will attempt a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), hold it at 0 for period of time in the range of .1ms to 1 second as defined by the Fault-Detect Recovery Constant register (FDRC registers 29-2Ah), then toggle it back to 1. This sequence is repeated as log as the fault indication exists. This feature is enabled by default but can be bypassed by setting the FDRB control bit to 1. 5.2 Configuration Register B(Address 01h)
D7 C2IM 1 D6 C1IM 0 D5 DSCKE 0 D4 SAIFB 0 D3 SAI3 0 D2 SAI2 0 D1 SAI1 0 D0 SAI0 0
5.2.1 Serial Data Interface Format
BIT 0 1 2 3 R/W R/W R/W R/W R/W RST 0 0 0 0 NAME SAI0 SAI1 SAI2 SAI3 DESCRIPTION Serial Audio Input Interface Format: Determines the interface format of the input serial digital audio interface.
5.2.2 Serial Data Interface The STA320 audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA320 always acts a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 inputs: left/right clock LRCKI, serial clock BICKI, and serial data 1 & 2 SDI12. The SAI register (Configuration Register B - 01h, Bits D3-D0) and the SAIFB register (Configuration Register B - 01h, Bit D4) are used to specify the serial data format. The default serial data format is I2S, MSBFirst. Available formats are shown in the tables and figure that follow. Table 11. Serial Data First Bit
SAIFB 0 1 Format MSB-First LSB-First
9/37
STA320
For example, SAI=1110 and SAIFB=1 would specify Right-Justified 16-bit data, LSB-First. Table 4 below lists the serial audio input formats supported by STA320 as related to BICKI = 32/48/64fs, where sampling rate fs = 32/44.1/48/88.2/96kHz. Table 12. Supported Serial Audio Input Formats
BICKI 32fs 1110 0100 0100 1000 0100 1100 0001 48fs 0101 1001 1101 0010 0110 1010 1110 0000 0100 1000 0000 1100 0001 64fs 0101 1001 1101 0010 0110 1010 1110 X X X X 0 1 X X X X X X X X X X X 0 1 X X X X X X X X SAI (3...0) 1100 SAIFB X Interface Format I2S 15bit Data Left/Right-Justified 16bit Data I2S 23bit Data I2S 20bit Data I2S 18bit Data MSB First I2S 16bit Data LSB First I2S 16bit Data Left-Justified 24bit Data Left-Justified 20bit Data Left-Justified 18bit Data Left-Justified 16bit Data Right-Justified 24bit Data Right-Justified 20bit Data Right-Justified 18bit Data Right-Justified 16bit Data I2S 24bit Data I2S 20bit Data I2S 18bit Data MSB First I2S 16bit Data LSB First I2S 16bit Data Left-Justified 24bit Data Left-Justified 20bit Data Left-Justified 18bit Data Left-Justified 16bit Data Right-Justified 24bit Data Right-Justified 20bit Data Right-Justified 18bit Data Right-Justified 16bit Data
5.2.3 Delay Serial Clock Enable
BIT 5 R/W R/W RST 0 NAME DSCKE DESCRIPTION Delay Serial Clock Enable: 0 - No serial clock delay 1 - Serial clock delay by 1 core clock cycle to tolerate anomalies in some I2S master devices
10/37
STA320
5.2.4 Channel Input Mapping
BIT 6 R/W R/W RST 0 NAME C1IM DESCRIPTION 0 - Processing channel 1 receives Left I2S Input 1 - Processing channel 1 receives Right I2S Input 0 - Processing channel 2 receives Left I2S Input 1 - Processing channel 2 receives Right I2S Input
7
R/W
1
C2IM
Each channel received via I2S can be mapped to any internal processing channel via the Channel Input Mapping registers. This allows for flexibility in processing. The default settings of these registers map each I2S input channel to its corresponding processing channel. 5.3 Configuration Register C(Address 02h)
D7 OCRB 1 D6 CSZ4 1 D5 CSZ3 0 D4 CSZ2 0 D3 CSZ1 0 D2 CSZ0 0 D1 OM1 1 D0 OM0 0
5.3.1 DDX Power Output Mode
BIT 0 1 R/W R/W R/W RST 0 1 NAME OM0 OM1 DESCRIPTION DDX Power Output Mode: Selects configuration of DDX output.
The DDX Power Output Mode selects how the DDX output timing is configured. Different power devices use different output modes. The STA50x or STA51x recommended use is OM = 10. Table 13. Output Modes
OM(1,0) 00 01 10 11 Output Stage - Mode STA50x/STA51x - Drop Compensation Discrete Output Stage - Tapered Compensation STA50x/STA51x - Full Power Mode Variable Drop Compensation (CSZx bits)
5.3.2 DDX Compensating Pulse Size Register
BIT 2 3 4 5 6 R/W R/W R/W R/W R/W R/W RST 0 0 0 0 1 NAME CSZ0 CSZ1 CSZ2 CSZ3 CSZ4 DESCRIPTION Contra Size Register: When OM(1,0) = 11, this register determines the size of the DDX compensating pulse from 0 clock ticks to 31 clock periods.
Table 14. Compensating Pulse Size
CSZ(4..0) 00000 00001 ... 11111 Compensating Pulse Size 0ns(0 tick) Compensating Pulse Size 10ns(1 tick) Clock period Compensating Pulse Size ... 310ns(31 tick) Clock period Compensating Pulse Size
11/37
STA320
5.3.3 Over-Current Warning Detect Adjustment Bypass
BIT 7 R/W R/W RST 1 NAME OCRB DESCRIPTION Over-Current-Warning Adjustment Bypass: 0 - Over-Current warning Adjustment enabled 1 - Over-Current warning Adjustment disabled
The OCDETECT input is used to indicate an Over-Current Warning condition. When OCDETECT is asserted (set to 0), the power control block will force a -3dB adjustment to the modulation limit in an attempt to eliminate the over-current warning condition. Once the over-current warning volume adjustment is applied, it remains in this state until reset is applied. 5.4 Configuration Register D(Address 03h)
D7 MME 0 D6 ZDE 1 D5 DRC 0 D4 BQL 0 D3 PSL 0 D2 DSPB 0 D1 DEMP 0 D0 HPB 0
5.4.1 High-Pass Filter Bypass
BIT 0 R/W R/W RST 0 NAME HPB DESCRIPTION High-Pass Filter Bypass Bit. Setting of one bypasses internal AC coupling digital high-pass filter
The STA320 features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage. When HPB=0, this filter is enabled 5.4.2 De-Emphasis
BIT 1 R/W R/W RST 0 NAME DEMP DE-emphasis 0 - No De-emphasis 1 - De-emphasis DESCRIPTION
Setting the DEMP bit enables de-emphasis on all channels 5.4.3 DSP Bypass
BIT 2 R/W R/W RST 0 NAME DSPB DESCRIPTION DSP bypass Bit: 0 - Normal Operation 1 - Bypass of Biquad and Bass/Treble Functionality
Setting the DSPB bit bypasses the EQ functionality of the STA320. 5.4.4 Post-Scale Link
BIT 3 R/W R/W RST 0 NAME PSL DESCRIPTION Post-Scale Link: 0 - Each Channel uses individual Post-Scale value 1 - Each Channel uses Channel 1 Post-Scale value
Post-Scale functionality can be used for power-supply error correction. For multi-channel applications running off the same power-supply, the post-scale values can be linked to the value of channel 1 for ease of use and update the values faster.
12/37
STA320
5.4.5 Biquad Coefficient Link
BIT 4 R/W R/W RST 0 NAME BQL DESCRIPTION Biquad Link: 0 - Each Channel uses coefficient values 1 - Each Channel uses Channel 1 coefficient values
For ease of use, all channels can use the biquad coefficients loaded into the Channel 1 Coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once. 5.4.6 Dynamic Range Compression/Anti-Clipping Bit
BIT 5 R/W R/W RST 0 NAME DRC DESCRIPTION Dynamic Range Compression/Anti-Clipping 0 - Limiters act in Anti-Clipping Mode 1 - Limiters act in Dynamic Range Compression Mode
Both limiters can be used in one of two ways, anti-clipping or dynamic range compression. When used in anticlipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level. 5.4.7 Zero-Detect Mute Enable
BIT 6 R/W R/W RST 1 NAME ZDE DESCRIPTION Zero-Detect Mute Enable: Setting of 1 enables the automatic zero-detect mute
Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled 5.4.8 Miami ModeTM Enable
BIT 7 R/W R/W RST 0 NAME MME DESCRIPTION Miami-Mode Enable: 0 - Sub Mix into Left/Right Disabled 1 - Sub Mix into Left/Right Enabled
5.5 Configuration Register E(Address 04h)
D7 SVE 1 D6 ZCE 1 D5 DCCV 0 D4 PWMS 0 D3 AME 0 D2 NSBW 0 D1 MPC 1 D0 MPCV 0
5.5.1 Max Power Correction Variable
BIT 0 R/W R/W RST 0 NAME MPCV DESCRIPTION Max Power Correction Variable: 0 - Use Standard MPC Coefficient 1 - Use MPCC bits for MPC Coefficient
5.5.2 Max Power Correction
BIT 1 R/W R/W RST 1 NAME MPC DESCRIPTION Max Power Correction: Setting of 1 enables STA50x/STA51x correction for THD reduction near maximum power output
13/37
STA320
Setting the MPC bit turns on special processing that corrects the STA50x/STA51x power device at high power. This mode should lower the THD+N of a full STA50x/STA51x DDX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered (OM(1,0) = 01). 5.5.3 Noise-Shaper Bandwidth Selection
BIT 2 R/W R/W RST 0 NAME NSBW DESCRIPTION Noise-Shaper Bandwidth Selection: 1 - 3rd order NS 0 - 4th order NS
5.5.4 AM Mode Enable
BIT 3 R/W R/W RST 0 NAME AME DESCRIPTION AM Mode Enable: 0 - Normal DDX operation. 1 - AM reduction mode DDX operation
The STA320 features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to ~83dB in this mode, which is still greater than the SNR of AM radio. 5.5.5 PWM Speed Mode
BIT 4 R/W R/W RST 0 NAME PWMS DESCRIPTION PWM Speed Selection: 0 - Normal Speed(384kHz) All Channels 1 - Odd Speed(341.3kHz) All Channels
5.5.6 Distortion Compensation Variable Enable
BIT 5 R/W R/W RST 0 NAME DCCV DESCRIPTION Distortion Compensation Variable Enable: 0 - Uses Preset DC Coefficient. 1 - Uses DCC Coefficient.
5.5.7 Zero-Crossing Volume Enable
BIT 6 R/W R/W RST 1 NAME ZCE DESCRIPTION Zero-Crossing Volume Enable: 1 - Volume adjustments will only occur at digital zero-crossings 0 - Volume adjustments will occur immediately
The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible. 5.5.8 Soft Volume Enable
BIT 7 R/W R/W RST 1 NAME SVE DESCRIPTION Soft Volume Enable: 1 - Volume adjustments ramp according to SVR settings 0 - Volume adjustments will occur immediately
5.6 Configuration Register F(Address 05h)
D7 EAPD 0 D6 PWDN 1 D5 ECLE 0 D4 LDTE 1 D3 BCLE 1 D2 IDE 1 D1 OCFG1P 0 D0 OCFG0 0
14/37
STA320
5.6.1 Output Configuration
BIT 0 1 R/W R/W R/W RST 0 0 NAME OCFG0 OCFG1 DESCRIPTION Selects the Output Configuration
Table 15. Output Configuration Engine Selection
OCFG(1..0) 00 Output Configuration 2 Channel (Full-Bridge) Power, 1 Channel DDX: 1A/1B 1A/1B w/ C1BO 0 2A/2B 2A/2B w/ C2BO 90/180 3A/3B 3A/3B w/ C3BO 45 2(Half-Bridge).1(Full-Bridge) On-Board Power: 1A 1A Binary 0 2A 1B Binary 90 3A/3B 2A/2B Binary 45 1A 3A Binary 0 2A 3B Binary 90 2 Channel (Full-Bridge) Power, 2 Channel Data-Out: 1A/1B 1A/1B Binary 0 2A/2B 2A/2B Binary 90 1A 3A Binary 0 2A 3B Binary 90 1 Channel Mono-Parallel: 3A 1A/1B w/ C3BO 45 3B 2A/2B w/ C3BO 45 3A/3B 3A/3B w/ C3BO 45 To the left of the arrow is the processing channel. Note that though the defaults are shown, using channel output mapping, any of the three processing channel outputs can be used for any of the three inputs
01
10
11
Note
5.6.2 Invalid Input Detect Mute Enable
BIT 2 R/W R/W RST 1 NAME IDE DESCRIPTION Invalid Input Detect Mute Enable: Setting of 1 enables the automatic invalid input detect mute
Setting the IDE bit enables this function, which looks at the input I2S data and will automatically mute if the signals are perceived as invalid. 5.6.3
BIT 3 R/W R/W RST 1 NAME BCLE DESCRIPTION Binary Output Mode Clock Loss Detection Enable
Detects loss of input MCLK in binary mode and will output 50% duty cycle. 5.6.4
BIT 4 R/W R/W RST 1 NAME LDTE DESCRIPTION LRCLK Double Trigger Protection Enable
Actively prevents double trigger of LRCLK. 5.6.5
BIT 5 R/W R/W RST 0 NAME ECLE DESCRIPTION Auto EAPD on Clock Loss
When active will issue a power device power down signal(EAPD) on clock loss detection
15/37
STA320
5.6.6 IC Power Down
BIT 7 R/W R/W RST 1 NAME PWDN DESCRIPTION IC Power Down: 0 - IC Power Down Low-Power Condition 1 - IC Normal Operation
The PWDN register is used to place the IC in a low-power state. When PWDN is written as 0, the output will begin a soft-mute. After the mute condition is reached, EAPD will be asserted to power down the power-stage, then the master clock to all internal hardware expect the I2C block will be gated. This places the IC in a very low power consumption stateConf 5.6.7 External Amplifier Power Down
BIT 7 R/W R/W RST 0 NAME EAPD DESCRIPTION External Amplifier Power Down: 0 -External Power Stage Power Down Active 1 -Normal Operation
5.7 Volume Control Registers(Addresses 06-0Ah) 5.7.1 Mute/QXpander RegisterI
D7 QFILT 0 D6 QXEN 0 D5 D4 TFRB 1 D3 C3M 0 D2 C2M 0 D1 C1M 0 D0 MMUTE 00
5.7.2 Thermal Fault(TWARN2) Recovery Bypass
BIT 4 R/W R/W RST 1 NAME TFRB DESCRIPTION Thermal-Fault (TWARN2) Recovery Bypass: 0 - Thermal fault recovery enabled 1 - Thermal fault recovery disabled
The TWARN2(Thermal Fault) input is used to indicate a thermal fault condition by an appropriate power device. When TWARN2 is asserted (set to 0), the power control block will attempt a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the power output block to begin recovery), hold it at 0 for period of time in the range of .1ms to 1 second as defined by the Fault-Detect Recovery Constant register (FDRC registers 29-2Ah), then toggle it back to 1. This sequence is repeated as log as the fault indication exists. This feature is disabled by default but can be enabled by setting the TFRB control bit to 0. 5.7.3 Qxpander Enable
BIT 6 R/W R/W RST 0 NAME QXEN DESCRIPTION Qxpander Enable: 0 - QXPander Disabled 1 - QXPander Enabled with proper security code
5.7.4 Qfilter Select
BIT 7 R/W R/W RST 0 NAME QFilt Qfilter Select 0 - Qfilter Used 1 - Simple LPF Used DESCRIPTION
16/37
STA320
5.7.5 Master Volume Register
D7 MV7 1 D6 MV6 1 D5 MV5 1 D4 MV4 1 D3 MV3 1 D2 MV2 1 D1 MV1 1 D0 MV0 1
5.7.6 Channel 1 Volume
D7 C1V7 0 D6 C1V6 1 D5 C1V5 1 D4 C1V4 0 D3 C1V3 0 D2 C1V2 0 D1 C1V1 0 D0 C1V0 0
5.7.7 Channel 2 Volume
D7 C2V7 0 D6 C2V6 1 D5 C2V5 1 D4 C2V4 0 D3 C2V3 0 D2 C2V2 0 D1 C2V1 0 D0 C2V0 0
5.7.8 Channel 3 Volume
D7 C3V7 0 D6 C3V6 1 D5 C3V5 1 D4 C3V4 0 D3 C3V3 0 D2 C3V2 0 D1 C3V1 0 D0 C3V0 0
The Volume structure of the STA320 consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5dB steps from +48dB to -80 dB. As an example if C3V = 00h or +48dB and MV = 18h or -12dB, then the total gain for channel 3 = +36dB. The Master Mute when set to 1 will mute all channels at once, whereas the individual channel mutes(CxM) will mute only that channel. Both the Master Mute and the Channel Mutes provide a "soft mute" with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate(~96kHz). A "hard mute" can be obtained by commanding a value of all 1's(255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel that whose total volume is less than -80dB will be muted. All changes in volume take place at zero-crossings when ZCE = 1(configuration register F) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE=0, volume updates will occur immediately. Table 16. Master Volume Offset as a function of MV(7..0).
MV(7..0) 00000000(00h) 00000001(01h) 00000010(02h) ... 01001100(4Ch) ... 11111110(FEh) 11111111(FFh) Volume Offset from Channel Value 0dB -0.5dB -1dB ... -38dB ... -127dB Hard Master Mute
17/37
STA320
Table 17. Channel Volume as a function of CxV(7..0)
CxV(7..0) 00000000(00h) 00000001(01h) 00000010(02h) ... 01100001(5Fh) 01100000(60h) 01011111(61h) ... 11010111(D7h) 11011000(D8h) 11011001(D9h) 11011010(DAh) ... 11101100(ECh) 11101101(EDh) ... 11111111(FFh) Volume +48dB +47.5dB +47dB ... +0.5dB 0dB -0.5dB ... +59.5dB -60dB -61dB -62dB ... -80 dB Hard Channel Mute ... Hard Channel Mute
5.8 Auto Mode Registers 5.8.1 AutoMode Register 1(Address 0x0B)
D7 AMPS 1 D6 D5 AMGC1 0 D4 AMGC2 0 D3 AMV2 0 D2 AMV1 0 D1 AMEQ1 0 D0 AMEQ0 0
Table 18. AutoMode EQ Settings
AMEQ(1,0) 00 01 10 11 User Programmable Preset EQ - PEQ bits Auto Volume Controlled Loudness Curve NA Mode(Biquad 2-6)
By setting AMEQ to any setting other than 00 enables AutoMode EQ. When set, biquads 1-4 are not user programmable. Any coefficient settings for these biquads will be ignored. Also when AutoMode EQ is used the pre-scale value for channels 1-6 becomes hard-set to -18dB, dependent upon the value of AMPS Table 19. AutoMode Volume Settings
AMV(1,0) 00 01 10 11 MVOL 0.5dB 256 Steps (Standard) MVOL Auto Curve 30 Steps MVOL Auto Curve 40 Steps MVOL Auto Curve 50 Steps Mode(MVOL)
18/37
STA320
Table 20. Automode Gain Compression/Limiters Selection
AMGC(1...0) 00 01 10 11 User Programmable GC AC No Clipping 2.1 AC Limited Clipping (10%) 2.1 DRC Nighttime Listening Mode 2.1 Mode
5.8.2
BIT 7 R/W R/W RST 1 NAME AMPS DESCRIPTION AutoMode Pre-Scale 0 - User Defined Pre-scale when AMEQ /= 00 1 - -18dB used for Pre-scale when AMEQ /= 00
5.8.3 AutoMode Register 2(Address 0x0C)
D7 XO3 0 D6 XO2 0 D5 XO1 0 D4 XO0 0 D3 AMAM2 0 D2 AMAM1 0 D1 AMAM0 0 D0 AMAME 0
5.8.4 AM Interference Frequency Switching
BIT 0 R/W R/W RST 0 NAME AMAME DESCRIPTION AutoMode AM Enable 0 - Switching Frequency Determined by PWMS Setting 1 - Switching Frequency Determined by AMAM Settings
Table 21. AutoMode AM Switching Frequency Selection
AMAM(2..0) 000 001 010 011 100 101 110 48kHz/96kHz Input Fs 0.535MHz - 0.720MHz 0.721MHz - 0.900MHz 0.901MHz - 1.100MHz 1.101MHz - 1.300MHz 1.301MHz - 1.480MHz 1.481MHz - 1.600MHz 1.601MHz - 1.700MHz 44.1kHz/88.2kHz Input Fs 0.535MHz - 0.670Mhz 0.671MHz - 0.800MHz 0.801MHz - 1.000MHz 1.001MHz - 1.180MHz 1.181MHz - 1.340Mhz 1.341MHz - 1.500MHz 1.501MHz - 1.700MHz
5.8.5 Bass Management Crossover
BIT 4 5 6 7 R/W R/W R/W R/W R/W RST 0 0 0 0 NAME XO0 XO1 XO2 XO3 DESCRIPTION Selects the Bass-Management Crossover Frequency. A 1st-Order Hi-Pass filter (channels 1 and 2) or a 2nd-Order Lo-pass filter (channel 3) at the selected frequency is performed.
19/37
STA320
Table 22. Bass Management Crossover Frequency
XO3..0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Crossover Frequency User -Defined 80 Hz 100 Hz 120 Hz 140 Hz 160 Hz 180 Hz 200 Hz 220 Hz 240 Hz 260 Hz 280 Hz 300 Hz 320 Hz 340 Hz 360 Hz
5.8.6 AutoModeRegister 3 (address 0x0D)
D7 D6 D5 D4 PEQ4 0 D3 PEQ3 0 D2 PEQ2 0 D1 PEQ1 0 D0 PEQ0 0
Table 23. Preset EQ Settings
PEQ(3..0) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Setting Flat Rock Soft Rock Jazz Classical Dance Pop Soft Hard Party Vocal Hip-Hop Dialog Bass-Boost #1 Bass-Boost #2 Bass-Boost #3 Loudness 1 (least boost) Loudness 2 Loudness 3 Loudness 4 Loudness 5 Loudness 6 Loudness 7 Loudness 8 Loudness 9 Loudness 10 Loudness 11 Loudness 12 Loudness 13 Loudness 14 Loudness 15 Loudness 16 (most boost)
20/37
STA320
5.9 Channel Configuration Registers(Addresses 0E-10h 5.9.1 )
D7 C1OM1 0 D6 C1OM0 0 D5 C1LS1 0 D4 C1LS0 0 D3 C1BO 0 D2 C1VPB 0 D1 C1EQBP 0 D0 C1TCB 0
5.9.2
D7 C2OM1 0 D6 C2OM0 0 D5 C2LS1 0 D4 C2LS0 0 D3 C2BO 0 D2 C2VPB 0 D1 C2EQBP 0 D0 C2TCB 0
5.9.3
D7 C3OM1 1 D6 C3OM0 0 D5 C3LS1 0 D4 C3LS0 0 D3 C2BO 0 D2 C3VPB 0 D1 D0
5.9.4 Tone Control Bypass Tone control(bass/treble) can be bypassed on a per channel basis for channels 1 and 2. CxTCB: 0 - Perform Tone Control on Channel X - normal operation 1 - Bypass Tone Control on Channel X
5.9.5 EQ Bypass EQ control can be bypassed on a per channel basis for channels 1 and 2. If EQ control is bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis, bass, treble in any combination) are bypassed for that channel. CxEQBP: 0 - Perform EQ on Channel X - normal operation 1 - Bypass EQ on Channel X
5.9.6 Volume Bypass Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel.
5.9.7 Binary Output Enable Registers Each individual channel output can be set to output a binary PWM stream. In this mode output A of a channel will be considered the positive output and output B is negative inverse. CxBO: 0 - DDX tri-state output - normal operation 1 - Binary OutputLimiter Select Limiter Selection can be made on a per-channel basis according to the channel limiter select bits.
21/37
STA320
Table 24. Channel Limiter Mapping as a function of CxLS bits
CxLS(1,0) 00 01 10 Channel Limiter Mapping Channel has limiting disabled Channel is mapped to limiter #1 Channel is mapped to limiter #2
5.9.8 Output Mapping Output mapping can be performed on a per channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs. Table 25. Channel Output Mapping as a function of CxOM bits.
CxOM(1,0) 00 01 10 Channel x Output Source Form Channel 1 Channel 2 Channel 3
5.10 Tone Control register (Address 11h) 5.10.1Tone Control
D7 TTC3 0 D6 TTC2 1 D5 TTC1 1 D4 TTC0 1 D3 BTC3 0 D2 BTC2 1 D1 BTC1 1 D0 BTC0 1
5.10.2Tone Control Boost/Cut as a function of BTC and TTC bits.
BTC(3..0)/TTC(3..0) 0000 0001 ... 0111 0110 0111 1000 1001 ... 1101 1110 1111 Boost/Cut -12dB -12dB ... -4dB -2dB 0dB +2dB +4dB ... +12dB +12dB +12dB
5.11 Dynamics Control Registers (Addresses 12-15h) 5.11.1Limiter 1 Attack/Release Rate
D7 L1A3 0 D6 L1A2 1 D5 L1A1 1 D4 L1A0 0 D3 L1R3 1 D2 L1R2 0 D1 L1R1 1 D0 L1R0 0
22/37
STA320
5.11.2Limiter 1 Attack/Release Threshold
D7 L1AT3 0 D6 L1AT2 1 D5 L1AT1 1 D4 L1AT0 0 D3 L1RT3 1 D2 L1RT2 0 D1 L1RT1 0 D0 L1RT0 1
5.11.3Limiter 2 Attack/Release Rate
D7 L2A3 0 D6 L2A2 1 D5 L2A1 1 D4 L2A0 0 D3 L2R3 1 D2 L2R2 0 D1 L2R1 1 D0 L2R0 0
5.11.4Limiter 2 Attack/Release Threshold
D7 L2AT3 0 D6 L2AT2 1 D5 L2AT1 1 D4 L2AT0 0 D3 L2RT3 1 D2 L2RT2 0 D1 L2RT1 0 D0 L2RT0 1
The STA320 includes 2 independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode or to actively reduce the dynamic range for a better listening environment such as a night-time listening mode which is often needed for DVDs. The two modes are selected via the DRC bit in Configuration Register F, bit 0 address 0x05. Each channel can be mapped to either limiter or not mapped, meaning that channel will clip when 0dBFS is exceeded. Each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then if needed adjust the gain of the mapped channels in unison. The limiter attack thresholds are determined by the LxAT registers. It is recommended in anti-clipping mode to set this to 0dBFS, which corresponds to the maximum unclipped output power of a DDX amplifier. Since gain can be added digitally within the STA320 it is possible to exceed 0dBFS or any other LxAT setting, when this occurs, the limiter, when active, will automatically start reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. The gain reduction occurs on a peak-detect algorithm. The release of limiter, when the gain is again increased, is dependent on a RMS-detect algorithm. The output of the volume/ limiter block is passed through a RMS filter. The output of this filter is compared to the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is again increased at a rate dependent upon the Release Rate register. The gain can never be increased past it's set value and therefore the release will only occur if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range, this is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound "lifeless". In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. Figure 5. Basic Limiter and Volume Flow Diagram.
Limiter
RMS
Gain/Volume
Input Gain Attenuation Saturation
Output
23/37
STA320
Table 26. Limiter Attack Rate as a function of LxA bits.
LxA(3..0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Attack Rate dB/ms 3.1584 2.7072 2.2560 1.8048 1.3536 0.9024 0.4512 0.2256 0.1504 0.1123 0.0902 0.0752 0.0645 0.0564 0.0501 0.0451 Slow Fast
Table 27. Limiter Release Rate as a function of LxR bits.
LxR(3..0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Release Rate dB/ms 0.5116 0.1370 0.0744 0.0499 0.0360 0.0299 0.0264 0.0208 0.0198 0.0172 0.0147 0.0137 0.0134 0.0117 0.0110 0.0104 Slow Fast
24/37
STA320
5.12 Anti-Clipping Mode Table 28. Limiter Attack Threshold as a function of LxAT bits (AC-Mode).
LxAT(3..0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AC(dB relative to FS) -12 -10 -8 -6 -4 -2 0 +2 +3 +4 +5 +6 +7 +8 +9 +10
Table 29. Limiter Release Threshold as a as a function of LxRT bits (AC-Mode).
LxRT(3..0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AC(dB relative to FS) - -29dB -20dB -16dB -14dB -12dB -10dB -8dB -7dB -6dB -5dB -4dB -3dB -2dB -1dB -0dB
25/37
STA320
5.13 Dynamic Range Compression Mode Table 30. Limiter Attack Threshold as a function of LxAT bits (DRC-Mode).
LxAT(3..0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DRC(dB relative to Volume) -31 -29 -27 -25 -23 -21 -19 -17 -16 -15 -14 -13 -12 -10 -7 -4
Table 31. Limiter Release Threshold as a as a function of LxRT bits (DRC-Mode).
LxRT(3..0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DRC(db relative to Volume + LxAT) - -38dB -36dB -33dB -31dB -30dB -28dB -26dB -24dB -22dB -20dB -18dB -15dB -12dB -9dB -6dB
26/37
STA320
5.14 User-Defined Coefficient Control Registers (Addresses 16-26h) 5.14.1Coefficient Address Register 1
D7 D6 D5 CFA5 0 D4 CFA4 0 D3 CFA3 0 D2 CFA2 0 D1 CFA1 0 D0 CFA0 0
5.14.2Coefficient b1Data Register Bits 23..16
D7 C1B23 0 D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0
5.14.3Coefficient b1Data Register Bits 15..8
D7 C1B15 0 D6 C1B14 0 D5 C1B13 0 D4 C1B12 0 D3 C1B11 0 D2 C1B10 0 D1 C1B9 0 D0 C1B8 0
5.14.4Coefficient b1Data Register Bits 7..0
D7 C1B7 0 D6 C1B6 0 D5 C1B5 0 D4 C1B4 0 D3 C1B3 0 D2 C1B2 0 D1 C1B1 0 D0 C1B0 0
5.14.5Coefficient b2 Data Register Bits 23..16
D7 C2B23 0 D6 C2B22 0 D5 C2B21 0 D4 C2B20 0 D3 C2B19 0 D2 C2B18 0 D1 C2B17 0 D0 C2B16 0
5.14.6Coefficient b2 Data Register Bits 15..8
D7 C2B15 0 D6 C2B14 0 D5 C2B13 0 D4 C2B12 0 D3 C2B11 0 D2 C2B10 0 D1 C2B9 0 D0 C2B8 0
5.14.7Coefficient b2 Data Register Bits 7..0
D7 C2B7 0 D6 C2B6 0 D5 C2B5 0 D4 C2B4 0 D3 C2B3 0 D2 C2B2 0 D1 C2B1 0 D0 C2B0 0
5.14.8Coefficient a1 Data Register Bits 23..16
D7 C1B23 0 D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0
5.14.9Coefficient a1 Data Register Bits 15..8
D7 C3B15 0 D6 C3B14 0 D5 C3B13 0 D4 C3B12 0 D3 C3B11 0 D2 C3B10 0 D1 C3B9 0 D0 C3B8 0
27/37
STA320
5.14.10Coefficient a1 Data Register Bits 7..0
D7 C3B7 0 D6 C3B6 0 D5 C3B5 0 D4 C3B4 0 D3 C3B3 0 D2 C3B2 0 D1 C3B1 0 D0 C3B0 0
5.14.11Coefficient a2 Data Register Bits 23..16
D7 C4B23 0 D6 C4B22 0 D5 C4B21 0 D4 C4B20 0 D3 C4B19 0 D2 C4B18 0 D1 C4B17 0 D0 C4B16 0
5.14.12Coefficient a2 Data Register Bits 15..8
D7 C4B15 0 D6 C4B14 0 D5 C4B13 0 D4 C4B12 0 D3 C4B11 0 D2 C4B10 0 D1 C4B9 0 D0 C4B8 0
5.14.13Coefficient a2 Data Register Bits 7..0
D7 C4B7 0 D6 C4B6 0 D5 C4B5 0 D4 C4B4 0 D3 C4B3 0 D2 C4B2 0 D1 C4B1 0 D0 C4B0 0
5.14.14Coefficient b0 Data Register Bits 23..16
D7 C5B23 0 D6 C5B22 0 D5 C5B21 0 D4 C5B20 0 D3 C5B19 0 D2 C5B18 0 D1 C5B17 0 D0 C5B16 0
5.14.15Coefficient b0 Data Register Bits 15..8
D7 C5B15 0 D6 C5B14 0 D5 C5B13 0 D4 C5B12 0 D3 C5B11 0 D2 C5B10 0 D1 C5B9 0 D0 C5B8 0
5.14.16Coefficient b0 Data Register Bits 7..0
D7 C5B7 0 D6 C5B6 0 D5 C5B5 0 D4 C5B4 0 D3 C5B3 0 D2 C5B2 0 D1 C5B1 0 D0 C5B0 0
5.14.17Coefficient Write Control Register
D7 D6 D5 D4 D3 RA 0 D2 R1 0 D1 WA 0 D0 W1 0
Coefficients for user-defined EQ, Mixing, Scaling, and Bass Management are handled internally in the STA320 via RAM. Access to this RAM is available to the user via an I2C register interface. A collection of I2C registers are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM. The following are instructions for reading and writing coefficients.
28/37
STA320
5.14.18Reading a coefficient from RAM

write 6-bits of address to I2C register 14h write 1 to R1 bit in I2C address 24h read top 8-bits of coefficient in I2C address 15h read middle 8-bits of coefficient in I2C address 16h read bottom 8-bits of coefficient in I2C address 17h
5.14.19Reading a set of coefficients from RAM

write 6-bits of address to I2C register 14h write 1 to RA bit in I2C address 24h read top 8-bits of coefficient in I2C address 15h read middle 8-bits of coefficient in I2C address 16h read bottom 8-bits of coefficient in I2C address 17h read top 8-bits of coefficient b2 in I2C address 18h read middle 8-bits of coefficient b2 in I2C address 19h read bottom 8-bits of coefficient b2 in I2C address 1Ah read top 8-bits of coefficient a1 in I2C address 1Bh read middle 8-bits of coefficient a1 in I2C address 1Ch read bottom 8-bits of coefficient a1 in I2C address 1Dh read top 8-bits of coefficient a2 in I2C address 1Eh read middle 8-bits of coefficient a2 in I2C address 1Fh read bottom 8-bits of coefficient a2 in I2C address 20h read top 8-bits of coefficient b0 in I2C address 21h read middle 8-bits of coefficient b0 in I2C address 22h read bottom 8-bits of coefficient b0 in I2C address 23h
5.14.20Writing a single coefficient to RAM

write 6-bits of address to I2C register 14h write top 8-bits of coefficient in I2C address 15h write middle 8-bits of coefficient in I2C address 16h write bottom 8-bits of coefficient in I2C address 17h write 1 to W1 bit in I2C address 24h
5.14.21Writing a set of coefficients to RAM

write 6-bits of starting address to I2C register 14h write top 8-bits of coefficient b1 in I2C address 15h write middle 8-bits of coefficient b1 in I2C address 16h write bottom 8-bits of coefficient b1 in I2C address 17h write top 8-bits of coefficient b2 in I2C address 18h write middle 8-bits of coefficient b2 in I2C address 19h
29/37
STA320

write bottom 8-bits of coefficient b2 in I2C address 1Ah write top 8-bits of coefficient a1 in I2C address 1Bh write middle 8-bits of coefficient a1 in I2C address 1Ch write bottom 8-bits of coefficient a1 in I2C address 1Dh write top 8-bits of coefficient a2 in I2C address 1Eh write middle 8-bits of coefficient a2 in I2C address 1Fh write bottom 8-bits of coefficient a2 in I2C address 20h write top 8-bits of coefficient b0 in I2C address 21h write middle 8-bits of coefficient b0 in I2C address 22h write bottom 8-bits of coefficient b0 in I2C address 23h write 1 to WA bit in I2C address 24h
The mechanism for writing a set of coefficients to RAM provides a method of updating the five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible unpleasant acoustic side-effects. When using this technique, the 6-bit address would specify the address of the biquad b1 coefficient (e.g. 0, 5, 10, ..., 20, ... 35 decimal), and the STA320 will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data. 5.14.22User-Defined EQ The STA320 provides the ability to specify four EQ filters (biquads) per each of the two input channels. The biquads use the following equation: Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n-1] + b2X[n-2] - 2(a1/2)Y[n-1] - a2Y[n-2] = b0X[n] + b1X[n-1] + b2X[n-2] - a1Y[n-1] - a2Y[n-2] where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed fractional multipliers, with coefficient values in the range of 800000h (-1) to 7FFFFFh (0.9999998808). Coefficients stored in the User Defined Coefficient RAM are referenced in the following manner: CxHy0 = b1/2 CxHy1 = b2 CxHy2 = -a1/2 CxHy3 = -a2 CxHy4 = b0/2 where x represents the channel and the y the biquad number. For example C2H41 is the b2 coefficient in the fourth biquad for channel 2. Additionally, the STA320 allows specification of a high-pass filter (processing channels 1 and 2) and a lo-pass filter (processing channel 3) to be used for bass-management crossover when the XO setting is "000" (userdefined). Both of these filters when defined by the user (rather than using the preset crossover filters) are 2nd order filters that use the biquad equation noted above. They are loaded into the C12H0-4 and C3Hy0-4 areas of RAM noted in the table below.
30/37
STA320
By default, all user-defined filters are "pass-thru" where all coefficients are set to 0, except the b0/2 coefficient which is set to 400000h (representing 0.5) 5.14.23Pre-Scale The STA320 provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 800000h = -1 and 7FFFFFh = 0.9999998808. The scale factor for this multiply is loaded into RAM using the same I2C registers as the biquad coefficients and the bass-management. All channels can use the channel 1 pre-scale factor by setting the Biquad link bit. By default, all pre-scale factors are set to 7FFFFFh. 5.14.24Post-Scale The STA320 provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel. This post-scaling is accomplished by using a 24-bit signed fractional multiplier, with 800000h = -1 and 7FFFFFh = 0.9999998808. The scale factor for this multiply is loaded into RAM using the same I2C registers as the biquad coefficients and the bass-management. This post-scale factor can be used in conjunction with an ADC equipped micro-controller to perform power-supply error correction. All channels can use the channel 1 post-scale factor by setting the post-scale link bit. By default, all post-scale factors are set to 7FFFFFh. 5.14.25Over-current Post-Scale The STA320 provides a simple mechanism for reacting to over-current detection in the power-device. When the ocdetect input is asserted, the over-current post-scale value is used in place of the normal post-scale value to provide output attenuation on all channels. The default setting provides 3dB of output attenuation when ocdetect is asserted. The amount of attenuation to be applied in this situation can be adjusted by modifying the Over-current Post-scale value. As with the normal post-scale, this scaling value is a 24-bit signed fractional multiplier, with 800000h = -1 and 7FFFFFh = 0.9999998808. By default, the over-current post-scale factor is set to 5A9DF7h. Once the overcurrent attenuation is applied, it remains until the device is reset.
31/37
STA320
Table 32. RAM Block for Biquads, Mixing, and Bass Management
Index (Decimal) 0 1 2 3 4 5 ... 19 20 21 ... 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Index (Hex) 00h 01h 02h 03h 04h 05h ... 13h 14h 15h ... 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh Channel 1 - Pre-Scale Channel 2 - Pre-Scale Channel 1 - Post-Scale Channel 2 - Post-Scale Channel 3 - Post-Scale Over-Current - Post-Scale Channel 1 - Mix 1 Channel 1 - Mix 2 Channel 2 - Mix 1 Channel 2 - Mix 2 Channel 3 - Mix 1 Channel 3 - Mix 2 UNUSED UNUSED Lo-Pass 2nd Order Filter for XO=000 ... Channel 2 - Biquad 4 Hi-Pass 2 Order Filter for XO=000
nd
Coefficient Channel 1 - Biquad 1 C1H10(b1/2) C1H11(b2) C1H12(a1/2) C1H13(a2) C1H14(b0/2) Channel 1 - Biquad 2 ... Channel 1 - Biquad 4 Channel 2 - Biquad 1 C1H20 ... C1H44 C2H10 C2H11 ... C2H44 C12H0(b1/2) C12H1(b2) C12H2(a1/2) C12H3(a2) C12H4(b0/2) C3H0(b1/2) C3H1(b2) C3H2(a1/2) C3H3(a2) C3H4(b0/2) C1PreS C2PreS C1PstS C2PstS C3PstS OCPstS C1MX1 C1MX2 C2MX1 C2MX2 C3MX1 C3MX2
Default 000000h 000000h 000000h 000000h 400000h 000000h ... 400000h 000000h 000000h ... 400000h 000000h 000000h 000000h 000000h 400000h 000000h 000000h 000000h 000000h 400000h 7FFFFFh 7FFFFFh 7FFFFFh 7FFFFFh 7FFFFFh 5A9DF7h 7FFFFFh 000000h 000000h 7FFFFFh 400000h 400000h
32/37
STA320
5.15 Variable Max Power Correction Registers (Addresses 27-29h): MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1 5.15.1.
D7 MPCC15 0 D6 MPCC14 0 D5 MPCC13 1 D4 MPCC12 0 D3 MPCC11 1 D2 MPCC10 1 D1 MPCC9 0 D0 MPCC8 1
5.15.2
D7 MPCC7 1 D6 MPCC6 1 D5 MPCC5 0 D4 MPCC4 0 D3 MPCC3 0 D2 MPCC2 0 D1 MPCC1 0 D0 MPCC0 0
5.16 Fault Detect Recovery Constant Registers(Addresses 2B-2Ch) FDRC bits specify the 16-bit Fault Detect Recovery time delay. When FAULT is asserted, the TRISTATE output will be immediately asserted lo and held lo for the time period specified by this constant. A constant value of 0001h in this register is ~.083ms. The default value of 000C specifies ~.1mSec. 5.16.1
D7 FDRC15 0 D6 FDRC14 0 D5 FDRC13 0 D4 FDRC12 0 D3 FDRC11 0 D2 FDRC10 0 D1 FDRC9 0 D0 FDRC8 0
5.16.2
D7 FDRC7 0 D6 FDRC6 0 D5 FDRC5 0 D4 FDRC4 0 D3 FDRC3 1 D2 FDRC2 1 D1 FDRC1 0 D0 FDRC0 0
5.17 Device Status Register(Address 2Dh)
D7 PLLUL D6 D5 D4 D3 OCWARN 1 D2 TFAULT 1 D1 FAULT 1 D0 TWARN 1
This register provides Fault and Thermal-Warning status information from the power control block. 5.18 Reserved Registers(Address 2Fh)
D7 RES 0 D6 RES 1 D5 RES 1 D4 RES 1 D3 RES 0 D2 RES 0 D1 RES 0 D0 RES 0
5.19 Reserved Registers(Addresses 30h-31h)
D7 RES D6 RES D5 RES D4 RES D3 RES D2 RES D1 RES D0 RES
33/37
STA320
5.19.1
D7 RES D6 RES D5 RES D4 RES D3 RES D2 RES D1 RES D0 RES
For details see next AN.
34/37
STA320
6 PACKAGE INFORMATION In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 6. SO28 Mechanical Data & Package Dimensions
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 1.27 16.51 7.6 1.27 0.291 0.016 0.1 0.35 0.23 0.5 45 (typ.) 18.1 10.65 0.697 0.394 0.050 0.65 0.299 0.050 0.713 0.419 mm TYP. MAX. 2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.013
OUTLINE AND MECHANICAL DATA
SO-28
8 (max.)
35/37
STA320
Table 33. Revision History
Date November 2004 Revision 1 First Issue Description of Changes
36/37
STA320
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners DDX is a trademark of Apogee tecnology inc. (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
37/37

▲Up To Search▲

Price & Availability of STA320

	To Download STA320 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .